AI Silicon Tracker
Every generation, what changed, and which AI numbers are actually real. Pick a company to follow one lineage, or compare all of them below.
7 of 12 companies here design AI silicon you cannot buy.
No company matches that.
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Amazon
AMZN
Trainium and Inferentia, the largest cloud-captive alternative to NVIDIA
Captive
5 chips
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AMD
AMD
Instinct accelerators on ROCm, the open alternative to CUDA
Merchant
8 chips
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Apple
AAPL
The Neural Engine, an on-device NPU at consumer scale
Captive
9 chips
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Broadcom
AVGO
Custom hyperscaler AI ASICs, and the Ethernet silicon that networks AI clusters
Custom
2 chips
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Google
GOOGL
The TPU, the leading non-NVIDIA AI training and inference accelerator
Captive
13 chips
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Intel
INTC
The incumbent x86 server CPU vendor rebuilding both an accelerator line and a US foundry
Merchant
2 chips
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MediaTek
2454
Dimensity NPU, high-volume edge AI across mainstream Android
Merchant
4 chips
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Microsoft
MSFT
Maia accelerators purpose-built for Azure inference
Captive
3 chips
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NVIDIA
NVDA
The merchant AI GPU standard, Tensor Core GPUs plus CUDA
Merchant
11 chips
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Qualcomm
QCOM
Hexagon NPU, on-device AI in Snapdragon, now scaled to rack-level inference
Merchant
9 chips
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Samsung
005930
Exynos NPUs, HBM memory, and being a leading-edge foundry that fabricates its rivals’ AI chips
Mixed
3 chips
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Tesla
TSLA
The in-car FSD inference computer, and Dojo as a cautionary tale in custom training hardware
Captive
2 chips
Every chip, all vendors
AMD Instinct
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
AMD |
May 2026 | TSMC 3nm | 6nm FinFET | PCIe Gen5 card, CDNA 4, air-cooled, 600 W | AbsoluteMXFP4: 4.6 PFLOPs | MXFP4 |
AMD |
Jan 2026 | TSMC 2nm | 3nm FinFET | CDNA 5 GPU (MI400 Series) in the Helios rack, 72 GPUs per rack | AbsolutePeak OCP MXFP4 Performance: 40.3 PFLOPs | MXFP4 |
AMD |
Nov 2025 | Not stated by AMD | MI400 Series GPU for HPC and sovereign AI, keeps hardware FP64 (288 TFLOPS) | Absolute9.2 PFLOPs FP4 | FP4/MXFP4 (engineering projection) |
AMD |
Jun 2025 | TSMC 3nm | 6nm FinFET | CDNA 4 GPU, OAM, liquid-cooled | AbsoluteMXFP4: 10.1 PFLOPs | MXFP4 |
AMD |
Jun 2024 | TSMC 5nm | 6nm FinFET | CDNA 3 GPU, OAM | AbsolutePeak FP8: 2.61 PFLOPs | FP8 (dense; 5.22 with sparsity) |
AMD |
Jun 2024 | TSMC 3nm | 6nm FinFET | CDNA 4 GPU, OAM, air-cooled | AbsoluteMXFP4: 9.2 PFLOPs | MXFP4 |
AMD |
Jun 2023 | TSMC 5nm | 6nm FinFET | CDNA 3 GPU, OAM, 153bn transistors | AbsolutePeak FP8 Performance (E5M2, E4M3): 2.61 PFLOPs | FP8 (dense; 5.22 with sparsity) |
AMD |
Jun 2023 | TSMC 5nm | 6nm FinFET | APU, 24 Zen 4 CPU cores plus CDNA 3 GPU on one package | AbsolutePeak FP8: 1.96 PFLOPs | FP8 (dense; 3.92 with sparsity) |
AWS Inferentia
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Amazon |
Nov 2022 | Not stated by AWS | Second-generation inference chip, 32 GB HBM | Absoluteup to 190 tera floating operations per second (TFLOPS) of FP16 performance per chip | FP16 |
Amazon |
Nov 2018 | Not stated by AWS | First-generation AWS machine-learning inference chip, 8 GB DDR4 | Absolute128 teraOPS on 8-bit integer (INT8) data per chip | INT8 |
AWS Trainium
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Amazon |
Dec 2024 | 3nm | Third-generation AWS training chip, AWS's first on 3nm | Absoluteup to 362 FP8 PFLOPs per 144-chip Trn3 UltraServer | FP8 (system level; no per-chip figure) |
Amazon |
Nov 2023 | Not stated by AWS | Second-generation AWS training chip | Absoluteup to 1.3 petaflops of dense FP8 compute per chip | FP8 (dense; 5.2 sparse) |
Amazon |
Dec 2020 | Not stated by AWS | First-generation AWS training chip, 32 GB per chip | Absoluteup to 3 petaflops of FP16/BF16 compute power per 16-chip Trn1 instance | FP16/BF16 (instance level, not per chip) |
Apple A-series
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Apple |
Sep 2026 | 2nm | Dual 16-core Neural Engine (32 cores total) | Relative only2x the compute power to run on-device AI models | Not disclosed |
Apple |
Sep 2025 | Third-generation 3nm | Neural Engine plus per-GPU-core Neural Accelerators | None publishedNo throughput figure published | Not disclosed |
Apple |
Sep 2025 | Not stated by Apple ? | 16-core Neural Engine plus per-GPU-core Neural Accelerators | Relative onlyUp to 3x the peak GPU compute over the previous generation (a GPU figure, not a Neural Engine one))) | Not disclosed |
Apple |
Sep 2024 | Second-generation 3nm | 16-core Neural Engine | Relative onlyRuns machine learning models up to 2x faster than A16 Bionic | Not disclosed |
Apple |
Sep 2024 | Second-generation 3nm | 16-core Neural Engine | Relative only17 per cent increase in total system memory bandwidth | Not disclosed |
Apple |
Sep 2023 | 3nm | 16-core Neural Engine | Relative onlyNeural Engine up to 2x faster | Not disclosed |
Apple |
Sep 2022 | Not stated by Apple ? | 16-core Neural Engine | AbsoluteNearly 17 trillion operations per second | Not stated |
Apple |
Sep 2021 | 5nm | 16-core Neural Engine | Absolute15.8 trillion operations per second | Not stated |
Apple |
Sep 2020 | 5nm | 16-core Neural Engine | Absolute11 trillion operations per second | Not stated |
Broadcom Jericho
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Broadcom |
Aug 2025 | 3nm | Router linking over a million XPUs across data centres | None publishedNo AI compute figure (networking chip) | Not applicable |
Broadcom Tomahawk
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Broadcom |
Jun 2025 | Not stated by Broadcom | 102.4 Tbps Ethernet switch for AI clusters | None publishedNo AI compute figure (networking chip) | Not applicable |
Exynos
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Samsung |
Dec 2025 | 2nm GAA | Exynos NPU | Relative onlyimproves generative AI performance by 113% compared to its predecessor | Not disclosed |
Samsung |
Jun 2025 | 3nm GAA | NPU with two 12K MAC clusters | Absoluteup to 59 trillion operations per second (TOPS) | Not disclosed |
Samsung |
Oct 2023 | 3rd-gen 4nm low-power | Exynos NPU | Relative only14.7x improvement in AI performance over the last generation | Not disclosed |
Google TPU
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
| Apr 2026 | Not stated by Google | Eighth-gen training TPU, up to 9,600 chips per superpod | AbsolutePeak FP4 12.6 PFLOPs per chip | FP4 | |
| Apr 2026 | Not stated by Google | Eighth-gen inference TPU, 384 MB on-chip SRAM | AbsolutePeak FP4 10.1 PFLOPs per chip | FP4 | |
| Apr 2025 | Not stated by Google | Seventh-generation Tensor Processing Unit built for inference | AbsoluteEach individual chip boasts peak compute of 4,614 TFLOPs. | FP8 (per Cloud TPU docs) | |
| May 2024 | Not stated by Google | Sixth-generation Tensor Processing Unit | Absolute918 TFLOPs BF16 per chip; 1,836 TOPs INT8 | BF16 | |
| Dec 2023 | Not stated by Google | Training-focused Tensor Processing Unit | Absolute459 TFLOPs BF16 per chip | BF16 (FP8 listed at the same value) | |
| Aug 2023 | Not stated by Google | Cost-focused Tensor Processing Unit | Absolute197 TFLOPs BF16 per chip; 393 TOPs INT8 | BF16 | |
| May 2021 | Not stated by Google | Google Tensor Processing Unit, fourth generation | Absolute275 teraflops (bf16 or int8) per chip | BF16 or INT8 |
Google Tensor
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
| Aug 2026 | 3nm (TSMC) | Tensor Processing Unit (TPU), co-designed with Google DeepMind | Relative only50% more TPU compute than Tensor G5; on-device AI tasks up to 3.5x faster using up to 3.5x less energy | Not disclosed | |
| Aug 2025 | 3nm (TSMC) | Tensor Processing Unit (TPU) | Relative onlyUp to 60% more powerful TPU than Tensor G4; on-device Gemini Nano 2.6x faster and 2x more efficient; context window 12,000 to 32,000 tokens | Not disclosed | |
| Aug 2024 | Not stated by Google ? | Tensor Processing Unit (TPU) | None publishedNo TPU figure published | Not disclosed | |
| Oct 2023 | Not stated by Google ? | Tensor Processing Unit (TPU) | Relative onlyRuns more than twice as many on-device models as Pixel 6; on-device generative AI 150x more complex than Pixel 7’s largest model | Not disclosed | |
| Oct 2022 | Not stated by Google ? | Tensor Processing Unit (TPU) | None publishedNo quantified claim published | Not disclosed | |
| Aug 2021 | Not stated by Google ? | Tensor Processing Unit (TPU) | None publishedNo figure published; qualitative only | Not disclosed |
Intel Gaudi
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Intel |
Apr 2024 | 5nm | AI accelerator, OAM and PCIe | Absolute1835 TFLOPS FP8 and BF16 matrix | FP8 and BF16 (dense or sparse not stated) |
Intel |
May 2022 | 7nm | Habana AI training and inference processor | Relative onlytwice the training throughput over the Nvidia A100-80GB GPU | Not disclosed |
MediaTek Dimensity
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
MediaTek |
Sep 2026 | 2nm | NPU 1090, second-gen Super Efficient NPU | Relative onlythe NPU 1090 delivers 51% higher LLM prefill performance, 55% higher Token generation per watt | Not disclosed |
MediaTek |
Sep 2025 | TSMC N3P | NPU 990 with Generative AI Engine 2.0, plus a separate compute-in-memory always-on NPU | Relative only2x compute; 100% faster 3B-parameter LLM output; 128K-token on-device context; BitNet 1.58-bit support. The widely cited 100 TOPS figure is not MediaTek’s; it traces to Counterpoint Research | BitNet 1.58-bit ternary |
MediaTek |
Oct 2024 | Second-generation TSMC 3nm | NPU 890 | Relative onlyUp to 80% faster LLM prompt performance and up to 35% more power efficient than Dimensity 9300 | Not disclosed |
MediaTek |
Nov 2023 | Third-generation TSMC 4nm | APU 790 | Relative only8x faster than the previous generation for Transformer models; supports LLMs at 1B, 7B and 13B parameters, scalable to 33B | Int and float, width not stated |
Microsoft Maia
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Microsoft |
Oct 2026 | TSMC N2P (compute chiplets) | Inference accelerator, eight HBM4 stacks, 950 W TDP, 96 per rack | Relative onlyup to 2.5x more performance per watt compared to Maia 200 | Not disclosed |
Microsoft |
Jan 2026 | TSMC 3nm | Inference SoC, 272 MB on-chip SRAM, 750 W | Absoluteover 10 petaFLOPS in 4-bit precision (FP4) per chip | FP4 (also over 5 PFLOPS FP8) |
Microsoft |
Nov 2023 | TSMC 5nm | First-gen Azure AI accelerator, about 820 mm2, 500 MB of L1/L2 | AbsolutePeak Dense Tensor POPS 6bit: 3, 9bit: 1.5, BF16: 0.8 | Dense (6-bit / 9-bit / BF16) |
NVIDIA Blackwell
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
NVIDIA |
Mar 2025 | TSMC 4NP | Enhanced fifth-gen Tensor Cores with 2x attention-layer acceleration, 208bn transistors across two dies | Absolute15 PetaFLOPS dense NVFP4 compute | NVFP4 (dense) |
NVIDIA GB200 Grace Blackwell Superchip NVIDIA |
Mar 2024 | TSMC 4NP (GPU dies) | One Grace CPU joined to two B200 GPUs over 900 GB/s NVLink-C2C | Absolute40 | 20 PFLOPS NVFP4 Tensor Core | NVFP4 (sparse | dense) |
NVIDIA |
Mar 2024 | TSMC 4NP | Fifth-gen Tensor Cores, second-gen Transformer Engine, 208bn transistors across two dies joined at 10 TB/s | Relative onlyBlackwell delivers 2.5x its predecessor's performance in FP8 for training, per chip, and 5x with FP4 for inference. | FP8 and FP4 (sparsity not stated) |
NVIDIA Hopper
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
NVIDIA |
Nov 2023 | Not stated by NVIDIA | Hopper GPU, the first with HBM3e (141 GB) | Absolute3,958 TFLOPS FP8 Tensor Core (H200 SXM) | FP8 (with sparsity) |
NVIDIA |
Mar 2022 | TSMC 4N | Fourth-gen Tensor Cores with the first Transformer Engine (FP8), 80bn transistors | Absolute3,958 teraFLOPS FP8 Tensor Core (H100 SXM) | FP8 (with sparsity) |
NVIDIA Jetson
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
NVIDIA Jetson AGX Thor (T5000) NVIDIA |
Mar 2024 | Not stated by NVIDIA | Blackwell GPU on the Thor SoC, 130 W, 128 GB LPDDR5X | Absoluteup to 2,070 FP4 teraflops of AI compute | FP4 (sparse) |
NVIDIA RTX Spark
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
NVIDIA |
May 2026 | Not stated by NVIDIA | NVIDIA Blackwell RTX GPU, 6,144 CUDA cores, fifth-generation Tensor Cores with FP4 precision; 20-core NVIDIA Grace CPU via NVLink-C2C | Absoluteup to 1 petaflop of FP4 AI performance | FP4 (sparse or dense not stated) |
NVIDIA Rubin
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
NVIDIA |
Mar 2026 | Not stated by NVIDIA | LP30 language processing unit, 500 MB on-chip SRAM per chip, 256 LPUs per rack | Absolute315 PFLOPS AI inference per LPX rack | FP8 (sparsity not stated) |
NVIDIA |
Jan 2026 | Not stated by NVIDIA | Third-gen Transformer Engine, 336bn transistors across two dies, NVLink 6 at 3.6 TB/s | AbsoluteRubin GPU delivers 50 petaflops of NVFP4 compute for AI inference | NVFP4 (sparse) |
NVIDIA |
Jan 2026 | Not stated by NVIDIA | One Vera CPU (88 custom Olympus Arm cores) joined to two Rubin GPUs over NVLink-C2C | Absolute100 PFLOPS NVFP4 inference | NVFP4 (sparse) |
NVIDIA |
Sep 2025 | Not stated by NVIDIA | Monolithic GPU for long-context inference, 128 GB GDDR7, hardware attention acceleration | Absoluteup to 30 petaflops of compute with NVFP4 precision | NVFP4 (sparsity not stated) |
Qualcomm Cloud AI
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Qualcomm |
Nov 2023 | Not stated by Qualcomm | PCIe card, 64 AI cores, 576 MB SRAM, 150 W | AbsoluteML capacity (INT8): 870 TOPs | INT8 |
Snapdragon 8
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Snapdragon 8 Elite Extreme Gen 6 Qualcomm |
Sep 2026 | 2nm | Reengineered Hexagon NPU | Relative only35% improved NPU performance | INT2 · INT4 · INT8 · INT16 · FP8 · FP16 |
Qualcomm |
Sep 2026 | 2nm | Hexagon NPU | Relative only14% improved NPU performance | Not disclosed |
Qualcomm |
Sep 2025 | 3nm | Hexagon NPU with Fused AI Accelerator | Relative only37% faster Hexagon NPU, 16% better performance per watt | INT2 · INT4 · INT8 · INT16 · FP8 · FP16 |
Qualcomm |
Oct 2024 | 3nm | Hexagon NPU | Relative only45% faster Hexagon NPU, 45% better performance per watt | INT4 · INT8 · INT16 · FP16 |
Qualcomm |
Oct 2023 | 4nm | Hexagon NPU | Relative onlyUp to 98% faster Hexagon NPU; on-device models up to 10B parameters at up to 20 tokens/sec (Llama 2 7B) | INT4 · INT8 · INT16 · FP16 |
Qualcomm |
Nov 2022 | 4nm | Hexagon NPU | Relative onlyUp to 4.35x faster AI performance than its predecessor | INT4 · INT8 · INT16 · FP16 |
Qualcomm |
Nov 2021 | 4nm | 7th Gen AI Engine with Hexagon processor | Relative onlyAI Engine up to 4x faster than predecessor | INT8 · INT16 · FP16 |
Snapdragon X
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Qualcomm |
Sep 2025 | Not stated by Qualcomm | Hexagon NPU | AbsoluteThe Qualcomm Hexagon NPU features 80 TOPS of AI processing | Not disclosed |
Tesla Dojo
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Tesla |
Aug 2021 | TSMC 7nm | Training die, 354 processing nodes, 440 MB SRAM | Absolute362 TFlops BF16/CFP8 | BF16/CFP8 |
Tesla FSD computer
| Chip | Announced | Node | Accelerator | What the vendor claims | Precision |
|---|---|---|---|---|---|
Tesla |
Apr 2019 | 14nm FinFET | Two neural network accelerators per chip, 96×96 MACs each | Absolute96×96 MACs (36.8 TOPS/NNA) | Not disclosed |
AI capability figures are reproduced exactly as each vendor published them. Most vendors publish no absolute throughput figure, and none of the mobile vendors state the numeric precision behind the figures they do give, which makes cross-vendor TOPS comparisons unreliable. Where a node is marked with a question mark, the vendor has not stated it.